196 search results - page 18 / 40 » Verification of timing Properties of VHDL |
FDL
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract-- Analog and Mixed Signal (AMS) designs are important integrated systems that link digital circuits to the analog world. Following the success of PSL verification methodol...
FMCAD
2007
Springer
13 years 11 months ago
2007
Springer
Parameterized heuristics abound in computer aided design and verification, and manual tuning of the respective parameters is difficult and time-consuming. Very recent results from ...
IJNSEC
2010
13 years 2 months ago
2010
In this paper, we construct two verifiable attribute-based encryption (VABE) schemes. One is with a single authority, and the other is with multi authorities. Not only our schemes ...
ATVA
2006
Springer
13 years 11 months ago
2006
Springer
Whereas partial order methods have proved their efficiency for the analysis of discrete-event systems, their application to timed systems remains a challenging research topic. Here...
FORMATS
2008
Springer
13 years 9 months ago
2008
Springer
Verification of partially synchronous distributed systems is difficult because of inherent concurrency and the potentially large state space of the channels. This paper identifies ...