196 search results - page 30 / 40 » Verification of timing Properties of VHDL |
SIGSOFT
2005
ACM
14 years 8 months ago
2005
ACM
Growing attention is being paid to application security at requirements engineering time. Confidentiality is a particular subclass of security concerns that requires sensitive inf...
ASE
2010
13 years 7 months ago
2010
Recent developments in runtime verification and monitoring show that parametric regular and temporal logic specifications can be efficiently monitored against large programs. Howev...
Publication
Modern hardware description languages support code-generation constructs like generate/endgenerate in Verilog. These constructs are intended to describe regular or parameterized ha...
SSS
2010
Springer
13 years 5 months ago
2010
Springer
Design and implementation of distributed algorithms often involve many subtleties due to their complex structure, non-determinism, and low atomicity as well as occurrence of unanti...
IJFCS
2006
13 years 7 months ago
2006
For successful software verification, model checkers must be capable of handling a large number of program variables. Traditional, BDD-based model checking is deficient in this re...