196 search results - page 31 / 40 » Verification of timing Properties of VHDL |
UML
2001
Springer
14 years 1 days ago
2001
Springer
The work presented here is part of a project that aims at the definition of a methodology for developing realtime software systems based on UML. In fact, being relatively easy to ...
FM
2003
Springer
14 years 25 days ago
2003
Springer
We present a novel application on model checking through SPIN as a means for verifying purely descriptive specifications written in TRIO, a first order, linear-time temporal logic ...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
We introduce a generic extension of the popular branching-time logic CTL which refines the temporal until and release operators with formal languages. For instance, a language may ...
ENTCS
2006
13 years 7 months ago
2006
It has been recognised for some time that there are close links between the various logics developed for the analysis of multi-agent systems and the many game-theoretic models dev...
PASTE
1998
ACM
13 years 11 months ago
1998
ACM
FLAVERS, a tool for verifying properties of concurrent systems, uses composite data flow analysis to incrementally improve the precision of the results of its verifications. Altho...