196 search results - page 3 / 40 » Verification of timing Properties of VHDL |
SDL
2001
13 years 9 months ago
2001
Abstract. We describe an approach for the verification of quantitative temporal properties of SDL specifications, which adapts techniques developed for timed automata [2]. With res...
RSP
2003
IEEE
14 years 26 days ago
2003
IEEE
This paper addresses the need for systematic verification of timing properties of real-time prototypes, which consist of timing constraints that must be satisfied at any given tim...
ENTCS
2006
13 years 7 months ago
2006
The application of formal methods to analog and mixed signal circuits requires efficient methods tructing abstractions of circuit behaviors. This paper concerns the verification o...
SIGSOFT
2007
ACM
14 years 8 months ago
2007
ACM
Model checking techniques have traditionally dealt with temporal logic languages and automata interpreted over -words, i.e., infinite in the future but finite in the past. However...
FORMATS
2009
Springer
13 years 11 months ago
2009
Springer
Abstract. Introducing a monitor on a system typically changes the system's behaviour by slowing the system down and increasing memory consumption. This may possibly result in ...