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» Verifying Correctness of Transactional Memories
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MICRO
2010
IEEE
170views Hardware» more  MICRO 2010»
13 years 4 months ago
Tolerating Concurrency Bugs Using Transactions as Lifeguards
Abstract--Parallel programming is hard, because it is impractical to test all possible thread interleavings. One promising approach to improve a multi-threaded program's relia...
Jie Yu, Satish Narayanasamy
FMCAD
2008
Springer
13 years 8 months ago
Word-Level Sequential Memory Abstraction for Model Checking
el Sequential Memory Abstraction for Model Checking Per Bjesse Advanced Technology Group Synopsys Inc. Many designs intermingle large memories with wide data paths and nontrivial c...
Per Bjesse
MEMOCODE
2010
IEEE
13 years 4 months ago
Proving transaction and system-level properties of untimed SystemC TLM designs
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
Daniel Große, Hoang M. Le, Rolf Drechsler
IASTEDSEA
2004
13 years 8 months ago
Java bytecode verification with dynamic structures
Java applets run on a Virtual Machine that checks code's integrity and correctness before execution using a module called Bytecode Verifier. Java Card technology allows Java ...
Cinzia Bernardeschi, Luca Martini, Paolo Masci
PLDI
2003
ACM
13 years 12 months ago
Automatically proving the correctness of compiler optimizations
We describe a technique for automatically proving compiler optimizations sound, meaning that their transformations are always semantics-preserving. We first present a domainspeci...
Sorin Lerner, Todd D. Millstein, Craig Chambers