1093 search results - page 123 / 219 » Verifying VLSI Circuits |
VLSID
1996
IEEE
14 years 1 months ago
1996
IEEE
Reduced Ordered Binary Decision Diagrams ROBDDs have traditionally been built in a bottom-up fashion. In this scheme, the intermediate peak memory utilization is often larger than...
VLSID
1993
IEEE
14 years 1 months ago
1993
IEEE
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
FCCM
2004
IEEE
14 years 20 days ago
2004
IEEE
Network Intrusion Detection and Prevention Systems (IDPS) use string matching to scan Internet packets for malicious content. Bloom filters offer a mechanism to search for a large...
ARVLSI
2001
IEEE
14 years 18 days ago
2001
IEEE
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
DAC
2005
ACM
13 years 11 months ago
2005
ACM
We present BonnPlace, a new VLSI placement algorithm that combines the advantages of analytical and partitioning-based placers. Based on (non-disjoint) placements minimizing the t...