For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchic...
As an efficient representation of Extended Finite State Machines, Multiway Decision Graphs (MDG) are suitable for automatic hardware verification of Register Transfer Level (RTL) ...
FPGA-based synthesis tools require information about behaviour and architectural to make effective use of the limited number of cells typically available. A hardware description l...
In this paper, two new dual-path based area efficient loop filter circuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25µ CS...
We have designed an adaptive analogue VLSI neuromorphic chip that will be used to interface MEM wind sensors to an insectinspired robot. The main chip components are a sensory inte...
Y. Zhang, A. Hamilton, R. Cheung, B. Webb, P. Argy...