1093 search results - page 28 / 219 » Verifying VLSI Circuits |
ICCAD
1993
IEEE
14 years 26 days ago
1993
IEEE
For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchic...
GLVLSI
2002
IEEE
14 years 1 months ago
2002
IEEE
As an efficient representation of Extended Finite State Machines, Multiway Decision Graphs (MDG) are suitable for automatic hardware verification of Register Transfer Level (RTL) ...
FCCM
1995
IEEE
14 years 8 days ago
1995
IEEE
FPGA-based synthesis tools require information about behaviour and architectural to make effective use of the limited number of cells typically available. A hardware description l...
GLVLSI
2007
IEEE
14 years 3 months ago
2007
IEEE
In this paper, two new dual-path based area efficient loop filter circuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25µ CS...
IWANN
2007
Springer
14 years 2 months ago
2007
Springer
We have designed an adaptive analogue VLSI neuromorphic chip that will be used to interface MEM wind sensors to an insectinspired robot. The main chip components are a sensory inte...