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» Verifying VLSI Circuits
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EH
2000
IEEE
123views Hardware» more  EH 2000»
14 years 1 months ago
The Test Vector Problem and Limitations to Evolving Digital Circuits
How do we know the correctness of an evolved circuit? While Evolutionary Hardware is exhibiting its effectiveness, we argue that it is very difficult to design a large-scale digit...
Kosuke Imamura, James A. Foster, Axel W. Krings
DDECS
2006
IEEE
101views Hardware» more  DDECS 2006»
14 years 2 months ago
Embedded Built-In-Test Detection Circuit for Radio Frequency Systems and Circuits
: An embedded rectifier-based Built-In-Test (BIT) detection circuit for the RF integrated circuits is proposed in this work, and charge pump rectifier is adopted to transform the R...
Guoyan Zhang, Ronan Farrell
MSE
1999
IEEE
204views Hardware» more  MSE 1999»
14 years 1 months ago
A PC-based Educational Tool for CMOS Integrated Circuit Design
This paper presents a PC based software running on PC dedicated to the training in sub-micron CMOS VLSI design. The software firstly consists in a HDL-based schematic editor with ...
Etienne Sicard, Chen Xi
DFT
2007
IEEE
104views VLSI» more  DFT 2007»
14 years 3 months ago
Reduction of Fault Latency in Sequential Circuits by using Decomposition
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky
DFT
2002
IEEE
121views VLSI» more  DFT 2002»
14 years 1 months ago
Testing Digital Circuits with Constraints
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...