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IEEEPACT
2007
IEEE
14 years 1 months ago
Error Detection Using Dynamic Dataflow Verification
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
Albert Meixner, Daniel J. Sorin
PARLE
1992
13 years 11 months ago
Characterizing the Paralation Model using Dynamic Assignment
Collection-oriented languages provide high-level constructs for describing computations over collections. These languages are becoming increasingly popular with the advent of massi...
Eric T. Freeman, Daniel P. Friedman
ICS
2003
Tsinghua U.
14 years 19 days ago
Inferential queueing and speculative push for reducing critical communication latencies
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
Ravi Rajwar, Alain Kägi, James R. Goodman
PDP
2010
IEEE
13 years 11 months ago
Malleable-Lab: A Tool for Evaluating Adaptive Online Schedulers on Malleable Jobs
—The emergence of multi-core computers has led to explosive development of parallel applications and hence the need of efficient schedulers for parallel jobs. Adaptive online sc...
Yangjie Cao, Hongyang Sun, Wen-Jing Hsu, Depei Qia...
EMSOFT
2007
Springer
13 years 11 months ago
Verification of device drivers and intelligent controllers: a case study
The soundness of device drivers generally cannot be verified in isolation, but has to take into account the reactions of the hardware devices. In critical embedded systems, interf...
David Monniaux