717 search results - page 68 / 144 » Virtual Circuit Switching |
FPGA
2010
ACM
14 years 4 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
—Dynamic programmable logic arrays (PLAs) which are built of the NOR–NOR structure, have been very popular in high performance design because of their high-speed and predictabl...
FOCS
1989
IEEE
13 years 11 months ago
1989
IEEE
In this paper, Boolean functions in ,4C0 are studied using harmonic analysis on the cube. The main result is that an ACO Boolean function has almost all of its “power spectrum”...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...
RSP
1998
IEEE
13 years 11 months ago
1998
IEEE
A technique to include virtual prototyping in the design cycle of complex digital modem ASICs is presented. It is innovating by using the same behavioral description for both the ...