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SBCCI
2005
ACM
276views VLSI» more  SBCCI 2005»
14 years 1 months ago
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congesti...
Aline Mello, Leonel Tedesco, Ney Calazans, Fernand...
AHS
2006
IEEE
100views Hardware» more  AHS 2006»
14 years 1 months ago
Wormhole Routing with Virtual Channels using Adaptive Rate Control for Network-on-Chip (NoC)
This paper presents a new approach in realizing Virtual Channels tailored for Network on Chip implementations. The technique makes use of a flow control mechanism based on adaptiv...
Ioannis Nousias, Tughrul Arslan
SBCCI
2005
ACM
114views VLSI» more  SBCCI 2005»
14 years 1 months ago
Traffic generation and performance evaluation for mesh-based NoCs
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
Leonel Tedesco, Aline Mello, Diego Garibotti, Ney ...
SIPS
2007
IEEE
14 years 1 months ago
Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency
System-on-Chip (SoC) designs become more complex nowadays. The communication between each processing element often suffers challenges due to the wiring problem. Networks-on-Chip (...
Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, An-Yeu Wu
ERSA
2006
161views Hardware» more  ERSA 2006»
13 years 8 months ago
A Parametric Study of Scalable Interconnects on FPGAs
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Mic...