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» Virtualized Architectural Heritage: New Tools and Techniques
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ASPDAC
2008
ACM
101views Hardware» more  ASPDAC 2008»
13 years 10 months ago
Interconnect modeling for improved system-level design optimization
Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level...
Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Ale...
RTSS
2005
IEEE
14 years 1 months ago
Event Count Automata: A State-Based Model for Stream Processing Systems
Recently there has been a growing interest in models and methods targeted towards the (co)design of stream processing applications; e.g. those for audio/video processing. Streams ...
Samarjit Chakraborty, Linh T. X. Phan, P. S. Thiag...
DAC
2007
ACM
14 years 8 months ago
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
WWW
2004
ACM
14 years 8 months ago
How to make a semantic web browser
Two important architectural choices underlie the success of the Web: numerous, independently operated servers speak a common protocol, and a single type of client--the Web browser...
D. A. Quan, R. Karger
DT
2000
88views more  DT 2000»
13 years 7 months ago
Postsilicon Validation Methodology for Microprocessors
f abstraction as applicable to break the problem's complexity, and innovating better techniques to address complexity of new microarchitectural features. Validation techniques...
Hemant G. Rotithor