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ICPP
2002
IEEE
14 years 2 months ago
ART: Robustness of Meshes and Tori for Parallel and Distributed Computation
In this paper, we formulate the array robustness theorems (ARTs) for efficient computation and communication on faulty arrays. No hardware redundancy is required and no assumptio...
Chi-Hsiang Yeh, Behrooz Parhami
INFOCOM
2002
IEEE
14 years 2 months ago
Avoiding Instability during Graceful Shutdown of OSPF
Abstract—Many recent router architectures decouple the routing engine from the forwarding engine, so that packet forwarding can continue even when the routing process is not acti...
Aman Shaikh, Rohit Dube, Anujan Varma
IPPS
2002
IEEE
14 years 2 months ago
Can User-Level Protocols Take Advantage of Multi-CPU NICs?
Modern high speed interconnects such as Myrinet and Gigabit Ethernet have shifted the bottleneck in communication from the interconnect to the messaging software at the sending an...
Piyush Shivam, Pete Wyckoff, Dhabaleswar K. Panda
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
14 years 2 months ago
Tarantula: A Vector Extension to the Alpha Architecture
Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processo...
Roger Espasa, Federico Ardanaz, Julio Gago, Roger ...
ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
14 years 2 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...
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