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DAC
1997
ACM
15 years 10 months ago
Toward Formalizing a Validation Methodology Using Simulation Coverage
The biggest obstacle in the formal verification of large designs is their very large state spaces, which cannot be handled even by techniques such as implicit state space travers...
Aarti Gupta, Sharad Malik, Pranav Ashar
SIGGRAPH
1997
ACM
15 years 10 months ago
A framework for realistic image synthesis
Our goal is to develop physically based lighting models and perceptually based rendering procedures for computer graphics that will produce synthetic images that are visually and ...
Donald P. Greenberg, Kenneth E. Torrance, Peter Sh...
EURODAC
1994
IEEE
221views VHDL» more  EURODAC 1994»
15 years 10 months ago
Implementation of a SDH STM-N IC for B-ISDN using VHDL based synthesis tools
payload. The current recommendations include SDH as the physical layer transmission standard. It is defined the BISDN user network interface (UNI) SDH-based at 155.52 Mbit/s, but t...
Juan Carlos Calderón, Enric Corominas, Jos&...
FOCS
1994
IEEE
15 years 10 months ago
Scheduling Multithreaded Computations by Work Stealing
This paper studies the problem of e ciently scheduling fully strict (i.e., wellstructured) multithreaded computations on parallel computers. A popular and practical method of sche...
Robert D. Blumofe
ASPLOS
1994
ACM
15 years 10 months ago
Reactive Synchronization Algorithms for Multiprocessors
Synchronization algorithms that are efficient across a wide range of applications and operating conditions are hard to design because their performance depends on unpredictable ru...
Beng-Hong Lim, Anant Agarwal
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