Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Bounding volume hierarchies (BVHs) are a popular acceleration structure choice for animated scenes rendered with ray tracing. This is due to the relative simplicity of refitting ...
Daniel Kopta, Thiago Ize, Josef B. Spjut, Erik Bru...
Assignment between two parties in a two-sided matching market has been one of the central questions studied in economics, due to its extensive applications, focusing on different...
Code quality and compilation speed are two challenges to JIT compilers, while selective compilation is commonly used to tradeoff these two issues. Meanwhile, with more and more Ja...
Yuan Zhang, Min Yang, Bo Zhou, Zhemin Yang, Weihua...
Process-level virtualization is increasingly being used to enhance the security of software applications from reverse engineering and unauthorized modification (called software p...