As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the e ects of memory access latency. In this paper, we introduce a nov...
Modern high-end machines feature multiple processor packages, each of which contains multiple independent cores and integrated memory controllers connected directly to dedicated ph...
: This paper presents our ongoing work on the analysis and optimization of cryptanalytic time-memory tradeoffs targeting the COPACOBANA architecture [KPP+ 06] as platform for the p...
Abstract. This work discusses the Memory Architecture for Reconfigurable Computers (MARC), a scalable, device-independent memory interface that supports both irregular (via configu...
To provide personalization and adaptivity in technology enhanced learning systems, the needs of learners have to be known by the system first. Detecting these needs is a challengin...