85 search results - page 13 / 17 » Worst Cases and Lattice Reduction |
TVLSI
2008
13 years 7 months ago
2008
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
Extensive research has proposed the use of multiple on-die power supplies (VDD) for reducing power consumption in CMOS circuits. We present a detailed study and design techniques ...
BIRTHDAY
2008
Springer
13 years 9 months ago
2008
Springer
The paper is an overview of a recently developed compilation data structure for graphical models, with specific application to constraint networks. The AND/OR Multi-Valued Decision...
SIROCCO
2004
13 years 8 months ago
2004
Path Layout is a fundamental graph problem in label switching protocols. This problem is raised in various protocols such as the traditional ATM protocol and MPLS which is a new l...
IJPP
2007
13 years 7 months ago
2007
As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival prob...