319 search results - page 39 / 64 » Worst-Case Analysis of Scheduling Heuristics of Parallel Sys... |
DATE
2011
IEEE
12 years 11 months ago
2011
IEEE
In order to meet performance/low energy/integration requirements, parallel architectures (multithreaded cores and multi-cores) are more and more considered in the design of embedd...
EMSOFT
2008
Springer
13 years 9 months ago
2008
Springer
In this paper we present a design space exploration flow to achieve energy efficiency for streaming applications on MPSoCs while meeting the specified throughput constraints. The ...
IEEEPACT
2005
IEEE
14 years 1 months ago
2005
IEEE
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
TCAD
2002
13 years 7 months ago
2002
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
RTAS
2006
IEEE
14 years 1 months ago
2006
IEEE
The rapid need for high bandwidth and low latency communication in distributed real-time systems is driving system architects towards high-speed switches developed for high volume...