291 search results - page 39 / 59 » Worst-case performance analysis of parallel, communicating s... |
TCAD
2002
13 years 7 months ago
2002
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
IPPS
2010
IEEE
13 years 4 months ago
2010
IEEE
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
FASE
2009
Springer
14 years 2 months ago
2009
Springer
Abstract. E-government services usually process large amounts of confidential data. Therefore, security requirements for the communication between components have to be adhered in...
PODC
2005
ACM
14 years 1 months ago
2005
ACM
Deadlock detection scheduling is an important, yet oft-overlooked problem that can significantly affect the overall performance of deadlock handling. An excessive initiation of ...
PADS
2004
ACM
14 years 1 months ago
2004
ACM
Parallel discrete event simulation techniques have enabled the realization of large-scale models of communication networks containing millions of end hosts and routers. However, t...