Sciweavers

399 search results - page 59 / 80
» XTR Implementation on Reconfigurable Hardware
Sort
View
ISCAS
2005
IEEE
129views Hardware» more  ISCAS 2005»
14 years 3 months ago
A reconfigurable architecture for scanning biosequence databases
—Unknown protein sequences are often compared to a set of known sequences (a database scan) to detect functional similarities. Even though efficient dynamic programming algorithm...
Timothy F. Oliver, Bertil Schmidt, Douglas L. Mask...
FPL
2008
Springer
86views Hardware» more  FPL 2008»
13 years 11 months ago
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors
In multi-context Dynamically Reconfigurable Processor Array (DRPA), the required number of contexts is often increased by those with low resource usage. In order to execute such c...
Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Ha...
IPPS
2000
IEEE
14 years 2 months ago
Augmenting Modern Superscalar Architectures with Configurable Extended Instructions
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...
Xianfeng Zhou, Margaret Martonosi
FCCM
2002
IEEE
126views VLSI» more  FCCM 2002»
14 years 2 months ago
Hyperspectral Image Compression on Reconfigurable Platforms
NASA’s satellites currently do not make use of advanced image compression techniques during data transmission to earth because of limitations in the available platforms. With th...
Thomas W. Fry, Scott Hauck
IEEECIT
2010
IEEE
13 years 8 months ago
SAT: A Stream Architecture Template for Embedded Applications
- The increase of embedded applications complexity has demanded hardware more flexible while providing higher performance. Reconfigurable architectures and stream processing have b...
Qianming Yang, Nan Wu, Mei Wen, Yi He, Huayou Su, ...