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ERSA
2004
129views Hardware» more  ERSA 2004»
13 years 11 months ago
A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs
Platform FPGAs incorporate many different components, such as processor core(s), reconfigurable logic, memory, etc., onto a single chip. When an application is synthesized on platf...
Jingzhao Ou, Viktor K. Prasanna
IJVR
2007
202views more  IJVR 2007»
13 years 9 months ago
Full Solid Angle Panoramic Viewing by Depth Image Warping on Field Programmable Gate Array
—To construct 3D virtual scenes from two-dimensional images with depth information, image warping techniques could be used. In this paper, a novel approach of cylindrical depth i...
Xiaoying Li, Baoquan Liu, Enhua Wu
IJES
2008
130views more  IJES 2008»
13 years 9 months ago
Deriving efficient control in Process Networks with Compaan/Laura
: At Leiden Embedded Research Center (LERC), we are building a tool chain called Compaan/Laura that allows us to map rapidly and efficiently signal processing applications written ...
Steven Derrien, Alexandru Turjan, Claudiu Zissules...
FPGA
2000
ACM
150views FPGA» more  FPGA 2000»
14 years 1 months ago
Programmable memory blocks supporting content-addressable memory
The Embedded System Block (ESB) of the APEX E programmable logic device family from Altera Corporation includes the capability of implementing content addressable memory (CAM) as ...
Frank Heile, Andrew Leaver, Kerry Veenstra
FPL
2008
Springer
207views Hardware» more  FPL 2008»
13 years 11 months ago
Bitstream compression techniques for Virtex 4 FPGAs
This paper examines the opportunity of using compression for accelerating the (re)configuration of FPGA devices, focusing on the choice of compression algorithms, and their hardwa...
Radu Stefan, Sorin Dan Cotofana