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CSSE
2008
IEEE
14 years 4 months ago
Generation of Executable Representation for Processor Simulation with Dynamic Translation
Instruction-Set Simulators (ISS) are indispensable tools for studying new architectures. There are several alternatives to achieve instruction set simulation, such as interpretive...
Jiajia Song, HongWei Hao, Claude Helmstetter, Vani...
ISPAN
2008
IEEE
14 years 4 months ago
A Taxonomy of Data Prefetching Mechanisms
Data prefetching has been considered an effective way to mask data access latency caused by cache misses and to bridge the performance gap between processor and memory. With hardw...
Surendra Byna, Yong Chen, Xian-He Sun
IWNAS
2008
IEEE
14 years 4 months ago
Software Barrier Performance on Dual Quad-Core Opterons
Multi-core processors based SMP servers have become building blocks for Linux clusters in recent years because they can deliver better performance for multi-threaded programs thro...
Jie Chen, William A. Watson III
SASP
2008
IEEE
164views Hardware» more  SASP 2008»
14 years 4 months ago
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications
This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The proces...
Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishito...
GRID
2007
Springer
14 years 4 months ago
An ActOn-based semantic information service for EGEE
— We describe an information service that aggregates metadata available in hundreds of information sources of the EGEE Grid infrastructure. It uses an ontology-based information ...
Wei Xing, Óscar Corcho, Carole A. Goble, Ma...