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ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
14 years 1 days ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
IEEEINTERACT
2003
IEEE
14 years 1 months ago
Compiler-Directed Resource Management for Active Code Regions
Recent studies on program execution behavior reveal that a large amount of execution time is spent in small frequently executed regions of code. Whereas adaptive cache management ...
Ravikrishnan Sree, Alex Settle, Ian Bratt, Daniel ...
TVLSI
2008
150views more  TVLSI 2008»
13 years 7 months ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz
SIGMETRICS
1999
ACM
14 years 1 days ago
On the Use of Trace Sampling for Architectural Studies of Desktop Applications
This paper examines the feasibility of performing architectural studies with trace sampling for a suite of desktop application traces on Windows NT. This paper makes three contrib...
Patrick Crowley, Jean-Loup Baer
ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
14 years 2 months ago
Interconnect design considerations for large NUCA caches
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
Naveen Muralimanohar, Rajeev Balasubramonian