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DATE
2009
IEEE
110views Hardware» more  DATE 2009»
14 years 2 months ago
Light NUCA: A proposal for bridging the inter-cache latency gap
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...
Darío Suárez Gracia, Teresa Monreal,...
ICCD
1999
IEEE
122views Hardware» more  ICCD 1999»
14 years 3 days ago
Design and Evaluation of a Selective Compressed Memory System
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim
HPCA
2002
IEEE
14 years 8 months ago
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....
ICS
2005
Tsinghua U.
14 years 1 months ago
A heterogeneously segmented cache architecture for a packet forwarding engine
As network traffic continues to increase and with the requirement to process packets at line rates, high performance routers need to forward millions of packets every second. Eve...
Kaushik Rajan, Ramaswamy Govindarajan
HOTI
2005
IEEE
14 years 1 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu