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ARC
2010
Springer
178views Hardware» more  ARC 2010»
14 years 4 months ago
An Analysis of Delay Based PUF Implementations on FPGA
Physical Unclonable Functions promise cheap, efficient, and secure identification and authentication of devices. In FPGA devices, PUFs may be instantiated directly from FPGA fabri...
Sergey Morozov, Abhranil Maiti, Patrick Schaumont
ARCS
2010
Springer
14 years 4 months ago
How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT
This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-ti...
Jörg Mische, Irakli Guliashvili, Sascha Uhrig...
ARC
2010
Springer
186views Hardware» more  ARC 2010»
14 years 1 months ago
Application-Specific Signatures for Transactional Memory in Soft Processors
As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchroni...
Martin Labrecque, Mark Jeffrey, J. Gregory Steffan
ARC
2010
Springer
126views Hardware» more  ARC 2010»
13 years 7 months ago
Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip
The SIMD parallel systems play a crucial role in the field of intensive signal processing. For most the parallel systems, communication networks are considered as one of the challe...
Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyse...
ENTCS
2002
103views more  ENTCS 2002»
13 years 9 months ago
Translation from timed Petri nets with intervals on transitions to intervals on places (with urgency)
Petri nets where, to my knowledge, the first theoretical model augmented with time constraints [Mer74], and the support of the first reachability algorithm of timed system [BM83, ...
Marc Boyer