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CGO
2008
IEEE
14 years 4 months ago
Prediction and trace compression of data access addresses through nested loop recognition
This paper describes an algorithm that takes a trace (i.e., a sequence of numbers or vectors of numbers) as input, and from that produces a sequence of loop nests that, when run, ...
Alain Ketterlin, Philippe Clauss
CGO
2008
IEEE
14 years 4 months ago
Spice: speculative parallel iteration chunk execution
The recent trend in the processor industry of packing multiple processor cores in a chip has increased the importance of automatic techniques for extracting thread level paralleli...
Easwaran Raman, Neil Vachharajani, Ram Rangan, Dav...
CGO
2008
IEEE
13 years 11 months ago
Comprehensive path-sensitive data-flow analysis
Data-flow analysis is an integral part of any aggressive optimizing compiler. We propose a framework for improving the precision of data-flow analysis in the presence of complex c...
Aditya V. Thakur, R. Govindarajan
CGO
2008
IEEE
14 years 4 months ago
Parallel-stage decoupled software pipelining
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...
Easwaran Raman, Guilherme Ottoni, Arun Raman, Matt...
CGO
2008
IEEE
14 years 4 months ago
Fast liveness checking for ssa-form programs
Liveness analysis is an important analysis in optimizing compilers. Liveness information is used in several optimizations and is mandatory during the code-generation phase. Two dr...
Benoit Boissinot, Sebastian Hack, Daniel Grund, Be...