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TC
1998
13 years 8 months ago
Optimizing the Instruction Cache Performance of the Operating System
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
Josep Torrellas, Chun Xia, Russell L. Daigle
DCC
1998
IEEE
14 years 1 months ago
Lossy Compression of Partially Masked Still Images
Books and magazines often contain pages containing audacious mixtures of color images and text. Our problem consists in coding the background colors of a such documents without wa...
Léon Bottou, Steven Pigeon
ICDCS
1998
IEEE
14 years 1 months ago
Fast, Optimized Sun RPC Using Automatic Program Specialization
Fast remote procedure call (RPC) is a major concern for distributed systems. Many studies aimed at efficient RPC consist of either new implementations of the RPC paradigm or manua...
Gilles Muller, Renaud Marlet, Eugen-Nicolae Volans...
IPPS
1998
IEEE
14 years 1 months ago
DEEP: A Development Environment for Parallel Programs
The use of the DEEP development environment to analyze parallel program performance is described. The full integrated environment contains tools for the creation, analysis and deb...
Brian Q. Brode, Chris R. Warber
IPPS
1998
IEEE
14 years 1 months ago
PACE: Processor Architectures for Circuit Emulation
We describe a family of reconfigurable parallel architectures for logic emulation. They are supposed to be applicable like conventional FPGAs, while covering a larger range of circ...
Reiner Kolla, Oliver Springauf