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169
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CODES
2009
IEEE
15 years 10 months ago
2009
IEEE
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
165
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CODES
2009
IEEE
15 years 8 months ago
2009
IEEE
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
145
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ICIP
2009
IEEE
16 years 5 months ago
2009
IEEE
The embedded-block coding with optimized truncation (EBCOT), which consists of a bit-plane coder (BPC) and a binary arithmetic coder (BAC), is the bottleneck in realizing a high-p...
126
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ICIP
2009
IEEE
16 years 5 months ago
2009
IEEE
In this paper, we perform double embedding in the quantization index modulation (QIM) framework where a single coefficient is modified twice, using two quantizers, to embed two bi...
114
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ICIP
2009
IEEE
16 years 5 months ago
2009
IEEE
Wyner-Ziv (WZ) coding of video utilizes simple encoders and highly complex decoders. A transcoder from a WZ codec to a traditional codec can potentially increase the range of appl...