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    Parallel Logic Simulation of VLSI Systems
    15 years 7 months ago
    Parallel Logic Simulation of VLSI Systems
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    Roger D. Chamberlain
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    97
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    DAC
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    Symbolic Modeling and Evaluation of Data Paths
    15 years 7 months ago
    Symbolic Modeling and Evaluation of Data Paths
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    Chuck Monahan, Forrest Brewer
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    99
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    DAC
    1995
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    Timing Driven Placement for Large Standard Cell Circuits
    15 years 7 months ago
    Timing Driven Placement for Large Standard Cell Circuits
    Download  www.cs.york.ac.uk
    William Swartz, Carl Sechen
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    91
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    DAC
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    A Fresh Look at Retiming Via Clock Skew Optimization
    15 years 7 months ago
    A Fresh Look at Retiming Via Clock Skew Optimization
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    Rahul B. Deokar, Sachin S. Sapatnekar
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    94
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    DAC
    1995
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    A Methodology for HW-SW Codesign in ATM
    15 years 7 months ago
    A Methodology for HW-SW Codesign in ATM
    Download  www.cecs.uci.edu
    Giovanni Mancini, Dave Yurach, Spiros Boucouris
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