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dac 1997
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An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment
15 years 7 months ago
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Stan Y. Liao, Steven W. K. Tjiang, Rajesh K. Gupta
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Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation
15 years 7 months ago
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Manish Pandey, Richard Raimi, Randal E. Bryant, Ma...
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Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis
15 years 7 months ago
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Claudio Passerone, Luciano Lavagno, Massimiliano C...
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Post-Layout Logic Restructuring for Performance Optimization
15 years 7 months ago
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cadlab.ece.ucsb.edu
Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Mal...
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1997
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Efficient Testing of Clock Regenerator Circuits in Scan Designs
15 years 7 months ago
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Rajesh Raina, Robert Bailey, Charles Njinda, Rober...
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