Variable ordering for BDDs has been extensively investigated. Recently, sampling based ordering techniques have been proposed to overcome problems with structure based static orde...
Yuan Lu, Jawahar Jain, Edmund M. Clarke, Masahiro ...
Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in today's gigahertz microprocessors c...
Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, And...
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
Image computation is the key step in fixpoint computations that are extensively used in model checking. Two techniques have been used for this step: one based on conjunction of the...
In-Ho Moon, James H. Kukula, Kavita Ravi, Fabio So...
This paper presents a D/A converter with a 14-bit intrinsic linearity in 0.5?m CMOS technology, which has been designed using a systematic design methodology for current-steering ...
Geert Van der Plas, Jan Vandenbussche, Walter Daem...