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dsn 2011
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2011
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Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors
14 years 2 months ago
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test.ict.ac.cn
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
Shuchang Shan, Yu Hu, Xiaowei Li
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2011
IEEE
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Computer Networks
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LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory
14 years 2 months ago
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www.cs.pitt.edu
Phase change memory (PCM) has emerged as a promising technology for main memory due to many advan tages, such as better scalability, non-volatility and fast read access. However,...
Lei Jiang, Yu Du, Youtao Zhang, Bruce R. Childers,...
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