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IPPS
2006
IEEE
14 years 1 months ago
Enhancing L2 organization for CMPs with a center cell
Chip multiprocessors (CMPs) are becoming a popular way of exploiting ever-increasing number of on-chip transistors. At the same time, the location of data on the chip can play a c...
Chun Liu, Anand Sivasubramaniam, Mahmut T. Kandemi...
CODES
2008
IEEE
14 years 2 months ago
Static analysis for fast and accurate design space exploration of caches
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
Yun Liang, Tulika Mitra
MICRO
2005
IEEE
113views Hardware» more  MICRO 2005»
14 years 1 months ago
Thermal Management of On-Chip Caches Through Power Density Minimization
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I....
WMPI
2004
ACM
14 years 1 months ago
A compressed memory hierarchy using an indirect index cache
Abstract. The large and growing impact of memory hierarchies on overall system performance compels designers to investigate innovative techniques to improve memory-system efficienc...
Erik G. Hallnor, Steven K. Reinhardt
FAST
2010
13 years 10 months ago
Extending SSD Lifetimes with Disk-Based Write Caches
We present Griffin, a hybrid storage device that uses a hard disk drive (HDD) as a write cache for a Solid State Device (SSD). Griffin is motivated by two observations: First, HDD...
Gokul Soundararajan, Vijayan Prabhakaran, Mahesh B...