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FDL
2007
IEEE
14 years 13 days ago
Transactor-based Formal Verification of Real-time Embedded Systems
With the increasing complexity of today's embedded systems, there is a need to formally verify such designs at mixed abstraction levels. This is needed if some compoe describ...
Daniel Karlsson, Petru Eles, Zebo Peng
FDL
2007
IEEE
14 years 2 months ago
Modelling Alternatives for Cycle Approximate Bus TLMs
Transaction level models (TLMs) can be constructed at t levels of abstraction, denoted as untimed (UT), cycle-approximate (CX), and cycle accurate (CA) in this paper. The choice o...
Martin Radetzki, Rauf Salimi Khaligh
FDL
2007
IEEE
14 years 2 months ago
Mapping Actor-Oriented Models to TLM Architectures
Actor-oriented modeling approaches are convenient for implementing functional models of embedded systems. Architectural models for heterogeneous system-on-chip architectures, howe...
Jens Gladigau, Christian Haubelt, Bernhard Niemann...
FDL
2007
IEEE
14 years 2 months ago
An Extension to VHDL-AMS for AMS Systems with Partial Differential Equations
Abstract This paper proposes VHDL-AMS syntax extensions that enable descriptions of AMS systems with partial differential equations. We named the extended language VHDL-AMSP. An im...
Leran Wang, Chenxu Zhao, Tom J. Kazmierski
FDL
2007
IEEE
14 years 13 days ago
Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL
Abstract-- Analog and Mixed Signal (AMS) designs are important integrated systems that link digital circuits to the analog world. Following the success of PSL verification methodol...
Ghiath Al Sammane, Mohamed H. Zaki, Zhi Jie Dong, ...