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ICPR
2004
IEEE
14 years 7 months ago
An FPGA-Based Architecture for Real Time Image Feature Extraction
We propose a novel FPGA-based architecture for the extraction of four texture features using Gray Level Cooccurrence Matrix (GLCM) analysis. These features are angular second mome...
Dimitrios E. Maroulis, Dimitrios K. Iakovidis, Dim...
SUTC
2010
IEEE
13 years 5 months ago
Hardware Implementation of Symbol Synchronization for Underwater FSK
—— Symbol synchronization is a critical component in the design of an underwater acoustic modem. Without accurate symbol synchronization, higher bit error rates incur thus reduc...
Ying Li, Xing Zhang, Bridget Benson, Ryan Kastner
APCCAS
2006
IEEE
271views Hardware» more  APCCAS 2006»
14 years 23 days ago
Fully-multiplexed First-order 3D IIR Frequency-Planar Filter Module
— A VLSI hardware architecture for the on-chip implementation of a first-order 3D IIR fully-multiplexed frequencyplanar filter module (FMFPM) is proposed. FMFPMs may be employed ...
Arjuna Madanayake, Leonard T. Bruton
FPL
2005
Springer
100views Hardware» more  FPL 2005»
14 years 7 days ago
HAIL: A Hardware-Accelerated Algorithm for Language Identification
A hardware-accelerated algorithm has been designed to automatically identify the primary languages used in documents transferred over the Internet. The algorithm has been implemen...
Charles M. Kastner, G. Adam Covington, Andrew A. L...
IJCNN
2000
IEEE
13 years 11 months ago
Hardware Implementation of a PCA Learning Network by an Asynchronous PDM Digital Circuit
We have fabricated a PCA (Principal Component Analysis) learning network in a FPGA (Field Programmable Gate Array) by using an asynchronous PDM (Pulse Density Modulation) digital ...
Yuzo Hirai, Kuninori Nishizawa