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GLVLSI
1999
IEEE
105views VLSI» more  GLVLSI 1999»
14 years 3 months ago
An Integrated Approach for Synthesizing LUT Networks
This paper presents a method for synthesizing lookup table (LUT) networks. The strategy employed by our method is very different from the strategies of previous methods; many deco...
Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
GLVLSI
1999
IEEE
59views VLSI» more  GLVLSI 1999»
14 years 3 months ago
Resonant Tunneling Technology for Mixed Signal and Digital Circuits in the 10-100 GHz Domain
The inherent bistability and picosecond time-scale switching of the resonant tunneling diode (RTD) provides an ideal element for the design of digital circuits and analog signal q...
T. P. E. Broekaert, B. Brar, F. Morris, A. C. Seab...
GLVLSI
1999
IEEE
81views VLSI» more  GLVLSI 1999»
14 years 3 months ago
Parallel Saturating Fractional Arithmetic Units
This paper describes the designs of a saturating adder, multiplier, single MAC unit, and dual MAC unit with one cycle latencies. The dual MAC unit can perform two saturating MAC o...
Navindra Yadav, Michael J. Schulte, John Glossner
GLVLSI
1999
IEEE
87views VLSI» more  GLVLSI 1999»
14 years 3 months ago
A Radix-16 SRT Division Unit with Speculation of the Quotient Digits
The speed of a divider based on a digit-recurrence algorithm depends mainly on the latency of the quotient digit generation function. In this paper we present an analytical approa...
Gianluca Cornetta, Jordi Cortadella
GLVLSI
1999
IEEE
91views VLSI» more  GLVLSI 1999»
14 years 3 months ago
A Novel Low Power Energy Recovery Full Adder Cell
A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this paper. The power consumption and general characteristics of the SERF adder...
R. Shalem, Lizy Kurian John, Eugene John