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GLVLSI
2007
IEEE
186views VLSI» more  GLVLSI 2007»
13 years 10 months ago
Block placement to ensure channel routability
Given a set of placed blocks, we present an algorithm that minimally spaces the blocks to ensure routability under several assumptions. By performing a binary search on total widt...
Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghav...
GLVLSI
2007
IEEE
173views VLSI» more  GLVLSI 2007»
13 years 10 months ago
Modeling and estimating leakage current in series-parallel CMOS networks
This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networ...
Paulo F. Butzen, André Inácio Reis, ...
GLVLSI
2007
IEEE
162views VLSI» more  GLVLSI 2007»
14 years 1 months ago
Utilizing custom registers in application-specific instruction set processors for register spills elimination
Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processo...
Hai Lin, Yunsi Fei
GLVLSI
2007
IEEE
167views VLSI» more  GLVLSI 2007»
14 years 4 months ago
A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS
A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CP...
Dariusz Kania
GLVLSI
2007
IEEE
135views VLSI» more  GLVLSI 2007»
14 years 4 months ago
Exact sat-based toffoli network synthesis
Compact realizations of reversible logic functions are of interest in the design of quantum computers. Such reversible functions are realized as a cascade of Toffoli gates. In th...
Daniel Große, Xiaobo Chen, Gerhard W. Dueck,...