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ICCAD
1993
IEEE
134views Hardware» more  ICCAD 1993»
14 years 3 months ago
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
In this paper, we present an integrated approach to synthesis and mapping to go beyond the combinatorial limit set up by the depth-optimal FlowMap algorithm. The new algorithm, na...
Jason Cong, Yuzheng Ding
ICCAD
1993
IEEE
100views Hardware» more  ICCAD 1993»
14 years 3 months ago
Macromodeling of the A.C. characteristics of CMOS Op-amps
An analytical-knowledge-based statistical method is developed to derive macromodels for the highly nonlinear A.C. response functions of CMOS Op-amp circuits. Simple circuit analys...
Pradip Mandal, V. Visvanathan
ICCAD
1993
IEEE
81views Hardware» more  ICCAD 1993»
14 years 3 months ago
Inverter minimization in multi-level logic networks
In this paper, we look at the problem of inverter minimization in multi-level logic networks. The network is specified in terms of a set of base functions and the inversion opera...
Alok Jain, Randal E. Bryant
ICCAD
1993
IEEE
104views Hardware» more  ICCAD 1993»
14 years 3 months ago
Parallel timing simulation on a distributed memory multiprocessor
Circuit simulation is one of the most computationally expensive tasks in circuit design and optimization. Detailed simulation at the level of precision of SPICE is usually perform...
Chih-Po Wen, Katherine A. Yelick
ICCAD
1993
IEEE
121views Hardware» more  ICCAD 1993»
14 years 3 months ago
Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures
For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchic...
Arjan J. van Genderen, N. P. van der Meijs