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ICCAD
1995
IEEE
77views Hardware» more  ICCAD 1995»
13 years 11 months ago
PARAS: system-level concurrent partitioning and scheduling
Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (calle...
Wing Hang Wong, Rajiv Jain
ICCAD
1995
IEEE
90views Hardware» more  ICCAD 1995»
13 years 11 months ago
An optimal algorithm for area minimization of slicing floorplans
The traditional algorithm of Stockmeyer for area minimization of slicing oorplans has time (and space) complexity O(n2 ) in the worst case, or O(nlogn) for balanced slicing. For ...
Weiping Shi
ICCAD
1995
IEEE
167views Hardware» more  ICCAD 1995»
13 years 11 months ago
A novel methodology for statistical parameter extraction
IC manufacturing process variations are typically expressed in terms of joint probability density functions (jpdf’s) or as worst case combinations/corners of the device model pa...
Kannan Krishna, Stephen W. Director
ICCAD
1995
IEEE
68views Hardware» more  ICCAD 1995»
13 years 11 months ago
Generating sparse partial inductance matrices with guaranteed stability
This paper proposes a definition of magnetic vector potential that can be used to evaluate sparse partial inductance matrices. Unlike the commonly applied procedure of discarding...
Byron Krauter, Lawrence T. Pileggi
ICCAD
1995
IEEE
163views Hardware» more  ICCAD 1995»
13 years 11 months ago
Signal integrity optimization on the pad assignment for high-speed VLSI design
Pad assignment with signal integrity optimization is very important for high-speed VLSI design. In this paper, an efficient method is proposed to effectively minimize both simulta...
Kai-Yuan Chao, D. F. Wong