This paper investigates the effect of the controller on the testability of sequential circuits composed of controllers and data paths. It is shown that even when both the controll...
With an ever-increasing portion of the delay in highspeed CMOS chips attributable to the interconnect, interconnect-circuit design automation continues to grow in importance. By t...
In a typical design
ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design specication either as a result o...
Abstract—We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematical...
Adnan Aziz, Felice Balarin, Robert K. Brayton, Alb...
: We study the minimum-cost bounded-skew routing tree problem under the Elmore delay model. We presenttwo approachesto construct bounded-skew routing trees: (i) the Boundary Mergin...
Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-...