Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
—As the 193nm lithography is likely to be used for 45nm and even 32nm processes, much more stringent requirement will be posed on Optical Proximity Correction (OPC) technologies....
—In the VLSI design process, a design implementation often needs to be corrected because of new specifications or design constraint violations. This correction process is referre...
Abstract— Nanoscale technology promises dramatically increased device density, but also decreased reliability. With bit error rates projected to be as high as 10%, designing a us...
Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Ryan ...
Modern IC designs have reached unparalleled levels of complexity, resulting in more and more bugs discovered after design tape-out However, so far only very few EDA tools for post...