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ICCD
1997
IEEE
90views Hardware» more  ICCD 1997»
13 years 11 months ago
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model
Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI tech...
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Ta...
ICCD
2004
IEEE
104views Hardware» more  ICCD 2004»
14 years 4 months ago
Exploiting Quiescent States in Register Lifetime
Large register file with multiple ports, but with a minimal access time, is a critical component in a superscalar processor. Analysis of the lifetime of a logical to physical reg...
Rama Sangireddy, Arun K. Somani
ICCD
2000
IEEE
135views Hardware» more  ICCD 2000»
14 years 4 months ago
A Methodology and Tool for Automated Transformational High-Level Design Space Exploration
el of abstraction by integrating a high-level estimation step. This results in a design loop which is tight led on high level of abstraction (called estimation loop in figure 1). ...
Joachim Gerlach, Wolfgang Rosenstiel
ICCD
2000
IEEE
93views Hardware» more  ICCD 2000»
14 years 4 months ago
Cheap Out-of-Order Execution Using Delayed Issue
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
J. P. Grossman
ICCD
2000
IEEE
79views Hardware» more  ICCD 2000»
14 years 4 months ago
Efficient Logic Optimization Using Regularity Extraction
This paper presents a new method to extract functionally equivalent structures from logic netlists. It uses a fast functional regularity extraction algorithm based on structural e...
Thomas Kutzschebauch