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ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
14 years 2 months ago
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper p...
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler,...
ISCA
2002
IEEE
80views Hardware» more  ISCA 2002»
14 years 2 months ago
A Large, Fast Instruction Window for Tolerating Cache Misses
Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instructi...
Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson K...
ISCA
2002
IEEE
128views Hardware» more  ISCA 2002»
14 years 2 months ago
Detailed Design and Evaluation of Redundant Multithreading Alternatives
Exponential growth in the number of on-chip transistors, coupled with reductions in voltage levels, makes each generation of microprocessors increasingly vulnerable to transient f...
Shubhendu S. Mukherjee, Michael Kontz, Steven K. R...
ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
14 years 2 months ago
A Scalable Instruction Queue Design Using Dependence Chains
Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...
Steven E. Raasch, Nathan L. Binkert, Steven K. Rei...
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
14 years 2 months ago
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, ...