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ISCAS
2003
IEEE
123views Hardware» more  ISCAS 2003»
14 years 3 months ago
Fast prototyping of reconfigurable architectures from a C program
Rapid evaluation and design space exploration at the algorithmic level are important issues in the design cycle. In this paper we propose an original area vs delay estimation meth...
Sebastien Bilavarn, Guy Gogniat, Jean Luc Philippe...
ISCAS
2003
IEEE
117views Hardware» more  ISCAS 2003»
14 years 3 months ago
Learning temporal correlations in biologically-inspired aVLSI
Temporally-asymmetric Hebbian learning is a class of algorithms motivated by data from recent neurophysiology experiments. While traditional Hebbian learning rules use mean firin...
Adria Bofill-i-Petit, Alan F. Murray
ISCAS
2003
IEEE
105views Hardware» more  ISCAS 2003»
14 years 3 months ago
Algorithmic partial analog-to-digital conversion in mixed-signal array processors
We present an algorithmic analog-to-digital converter (ADC) architecture for large-scale parallel quantization of internally analog variables in externally digital array processor...
Roman Genov, Gert Cauwenberghs
ISCAS
2003
IEEE
125views Hardware» more  ISCAS 2003»
14 years 3 months ago
Low noise amplifier design for ultra-wideband radio
A new theoretical approach for designing a low-noise amplifier (LNA) for the ultra-wideband (UWB) radio is presented. Unlike narrowband systems, the use of the noise figure (NF) p...
Jongrit Lerdworatawee, Won Namgoong
ISCAS
2003
IEEE
93views Hardware» more  ISCAS 2003»
14 years 3 months ago
A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform
In this paper, we propose a fast pipeline VLSI architecture for 1D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predict...
Bing-Fei Wu, Chung-Fu Lin