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ISCAS
2005
IEEE
163views Hardware» more  ISCAS 2005»
14 years 1 months ago
A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip
— We propose a new crossbar switch structure with adaptive bandwidth control. In a complex SoC design, the proposed crossbar switch efficiently incorporates various IPs with diff...
Donghyun Kim, Kangmin Lee, Se-Joong Lee, Hoi-Jun Y...
ISCAS
2005
IEEE
168views Hardware» more  ISCAS 2005»
14 years 1 months ago
Is home network application acceptable or not?
— Application of the home network is the most important factor to make the future home network environment pervasive. Although home network environment allows us to control appli...
Ikuo Keshi, Yumi Shiraishi, Hiroaki Niwamoto, Mino...
ISCAS
2005
IEEE
113views Hardware» more  ISCAS 2005»
14 years 1 months ago
On the robustness of an analog VLSI implementation of a time encoding machine
Abstract— Time encoding is a mechanism for representing the information contained in a continuous time, bandlimited, analog signal as the zero-crossings of a binary signal. Time ...
Peter R. Kinget, Aurel A. Lazar, Laszlo T. Toth
ISCAS
2005
IEEE
153views Hardware» more  ISCAS 2005»
14 years 1 months ago
A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher
—A high-throughput hardware architecture and FPGA implementation of the 64-bit NESSIE proposal, MISTY1 block cipher, is presented in this paper. This architecture, in contrast to...
Paris Kitsos, Michalis D. Galanis, Odysseas G. Kou...
ISCAS
2005
IEEE
247views Hardware» more  ISCAS 2005»
14 years 1 months ago
Digital signal processing engine design for polar transmitter in wireless communication systems
Polar modulation techniques offer the capability of multimode wireless system and the potential for the high efficiency Power Amplifier (PA). This paper describes a new design of D...
Hung Yang Ko, Yi-Chiuan Wang, An-Yeu Wu