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ISQED
2003
IEEE
14 years 3 months ago
2003
IEEE
This paper proposes a new clocking strategy for dynamic circuit. It provides faster performance and smaller area than conventional clocking scheme. The proposed clocking scheme fo...
ISQED
2003
IEEE
14 years 3 months ago
2003
IEEE
A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there...
ISQED
2003
IEEE
14 years 3 months ago
2003
IEEE
— The design of an efficient monolithic buck converter is presented in this paper. A low swing MOSFET gate drive technique is proposed that improves the efficiency characteristic...
ISQED
2003
IEEE
14 years 3 months ago
2003
IEEE
As the portion of coupling capacitance increases in smaller process geometries, accurate coupled noise analysis is becoming more important in current design methodologies. We prop...
ISQED
2003
IEEE
14 years 3 months ago
2003
IEEE
This paper presents an electrical and thermal performance analysis of System-in-a-Package (SiP) memory/logic implementation platform based on ChipLaminate-Chip (CLC) technology. I...