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NOCS
2008
IEEE
15 years 10 months ago
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration
Bin Li, Li-Shiuan Peh, Priyadarsan Patra
103
Voted
NOCS
2008
IEEE
15 years 10 months ago
Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture
Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, ...
101
Voted
NOCS
2008
IEEE
15 years 10 months ago
A Network of Time-Division Multiplexed Wiring for FPGAs
Rosemary M. Francis, Simon W. Moore, Robert D. Mul...
93
Voted
NOCS
2008
IEEE
15 years 10 months ago
Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip
Andreas Hansson, Maarten Wiggers, Arno Moonen, Kee...