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DAC
2005
ACM
13 years 8 months ago
Normalization at the arithmetic bit level
We propose a normalization technique for verifying arithmetic circuits in a bounded model checking environment. Our technique operates on the arithmetic bit level (ABL) descriptio...
Markus Wedler, Dominik Stoffel, Wolfgang Kunz
ISCAS
2005
IEEE
107views Hardware» more  ISCAS 2005»
14 years 9 days ago
Parameter domain pruning for improving convergence of synthesis algorithms
— This paper presents a parameter domain pruning method. Parameter domain pruning aims to identify parameter sub-domains that are more likely to produce feasible and good design ...
Hua Tang, Alex Doboli
GLVLSI
2005
IEEE
85views VLSI» more  GLVLSI 2005»
14 years 10 days ago
Utilizing don't care states in SAT-based bounded sequential problems
Boolean Satisfiability (SAT) solvers are popular engines used throughout the verification world. Bounded sequential problems such as bounded model checking and bounded sequentia...
Sean Safarpour, Görschwin Fey, Andreas G. Ven...
STACS
2005
Springer
14 years 5 days ago
Algorithmics in Exponential Time
Exponential algorithms, i.e. algorithms of complexity O(cn ) for some c > 1, seem to be unavoidable in the case of NP-complete problems (unless P=NP), especially if the problem ...
Uwe Schöning
CHARME
2005
Springer
133views Hardware» more  CHARME 2005»
14 years 7 days ago
Symbolic Partial Order Reduction for Rule Based Transition Systems
Partial order (PO) reduction methods are widely employed to combat state explosion during model-checking. In this paper, we develop a partial order reduction algorithm for rule-bas...
Ritwik Bhattacharya, Steven M. German, Ganesh Gopa...