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    SCP
    1998
    163views more  SCP 1998»
    Computing with Continuous Change
    13 years 8 months ago
    Computing with Continuous Change
    Download  www-cs-students.stanford.edu
    A central challenge in computer science and knowledge representation is the integration of conceptual frameworks for continuous and discrete change, as exemplified by the theory ...
    Vineet Gupta, Radha Jagadeesan, Vijay A. Saraswat
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    SIAMCOMP
    1998
    117views more  SIAMCOMP 1998»
    The Queue-Read Queue-Write PRAM Model: Accounting for Contention in Parallel Algorithms
    13 years 8 months ago
    The Queue-Read Queue-Write PRAM Model: Accounting for Contention in Parallel Algorithms
    Download  theory.stanford.edu
    This paper introduces the queue-read, queue-write (qrqw) parallel random access machine (pram) model, which permits concurrent reading and writing to shared memory locations, but ...
    Phillip B. Gibbons, Yossi Matias, Vijaya Ramachand...
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    SOFTWARE
    1998
    192views Applied Computing» more  SOFTWARE 1998»
    Interrupts: Just a Minute Never Is
    13 years 8 months ago
    Interrupts: Just a Minute Never Is
    Download  interruptions.net
    development is a highly abstract process that requires intense concentration. The authors show that interrupting this process can significantly reduce a developer’s efficiency an...
    Rini van Solingen, Egon Berghout, Frank van Latum
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    TC
    1998
    177views Information Technology» more  TC 1998»
    Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices
    13 years 8 months ago
    Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices
    Download  www.eecs.umich.edu
    —This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs)...
    Alejandro F. González, Pinaki Mazumder
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    TC
    1998
    91views Information Technology» more  TC 1998»
    Optimizing the Instruction Cache Performance of the Operating System
    13 years 8 months ago
    Optimizing the Instruction Cache Performance of the Operating System
    Download  iacoma.cs.uiuc.edu
    —High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
    Josep Torrellas, Chun Xia, Russell L. Daigle
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