This paper describes a tiling technique that can be used by application programmers and optimizing compilers to obtain I/O-efficient versions of regular scientific loop nests. Due ...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
TCP has been the dominant transport protocol over the global Internet, and its performance over a hybrid wireless/wireline network has attracted much attention in recent years. Thi...
The high-performance supercomputers will consist of several millions of CPUs in the next decade. The interconnection networks in such supercomputers play an important role for achi...
Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter [?]. More than a decade of architectural a...
Historically, compilers have operated by applying a fixed set of optimizations in a predetermined order. We call such an ordered list of optimizations a compilation sequence. This...
Keith D. Cooper, Devika Subramanian, Linda Torczon